1. Field of the Invention
The present invention relates to a thin film transistor for use in an active matrix liquid crystal display panel, an input/output device as of a contact-type image sensor, a portable electronic instrument, etc., and also to a method for manufacturing such thin film transistor.
2. Description of the Related Art
In forming a thin film transistor (hereinafter also called TFT) on a substrate of glass, the hydrogenated amorphous silicon semiconductor TFT technology and the polysilicon TFT technology are currently available as typical technologies. According to the former, the maximum temperature of the fabrication process is about 300xc2x0, and a carrier mobility of approximately 1 cm2/Vsec is obtained. According to the latter, using a high-temperature process analogous to the LSI process of about 1000xc2x0 C. using a substrate as of quartz, a carrier mobility of 30 to 100 1 cm2/Vsec can easily be obtained. In case of the high carrier mobility, when the thin film transistor is applied to, for example, a liquid crystal display, it is possible to simultaneously form on the same glass substrate a pixel TFT driving each pixel and even a peripheral driving circuit section as well. The resulting thin film transistor is inexpensive and small-sized.
However, in the polysilicon TFT technology, inexpensive low-melting-point glass, which is originally suitable to the former process, cannot be employed in the above-mentioned high-temperature process. For decreasing the temperature of the polysilicon TFT process, the laser crystallization technology, the low temperature film (gate insulating film) formation technology and the low temperature interface (of insulating film and silicon) formation technology are sought after. Studies and developments have been made to solve the foregoing problems. To this end, IEEE ELECTRON DEVICE LETTERS, Vol. 15, No. 2, page 69, xe2x80x9cHigh Performance Polycrystalline Silicon Thin Film Transistor Fabricated Using Remote Plasma CVD of SiO2,xe2x80x9d (M. Sekiya, et al.) discloses a hybrid fabricating apparatus and method composed of two different fabrication processes: the laser crystallization for forming a good interface between an insulating film and a silicon layer at low temperature, and the remote plasma CVD for forming a silicon dioxide film. This hybrid concept aims to maintain a good insulating-film-and-silicon interface at low temperature by forming a gate insulating film on a high-quality polysilicon film, which is formed by the excimer laser crystallization without exposure to atmosphere, and by keeping the interface well clean. In this technological paper, as a polysilicon TFT fabrication process, the following process flow was proposed. After a source-and-drain layer (20 nm thick) has been formed in an island shape, a silicon layer (20 nm thick) is formed. Then, laser crystallization, hydrogen treatment (which comes immediately after laser crystallization) and fabrication of a first insulating film (SiO2, 100 nm thick) take place in succession. As a result, a good insulating-film-and-silicon interface is obtained at low temperature. After that, the silicon layer is patterned in an island shape. In addition, a second insulating film (100 nm thick) is formed to secure silicon-electrode isolation.
In the meantime, as reduction of the power output and the driving voltage of a liquid display, an image sensor or the like has been practical, it is increasingly becoming necessary not only to improve the performance of TFT by cleaning the interface but also to reduce the operating threshold voltage of TFT. And it has turned out from recent studies that thinning the gate insulating film is effective for reduction of the operating threshold voltage; such thinning method applied to a planar thin film transistor will now be described with reference to FIGS. 9(a) to 9(c) of the accompanying drawings. FIG. 9(a) is a top plan view of the planar thin film transistor, FIG. 9(b) is a cross-sectional view taken alone line A-Axe2x80x2 of FIG. 9(a), and FIG. 9(c) is a cross-sectional view taken along line B-Bxe2x80x2 of FIG. 9(a). A first insulating film 5 patterned in an island shape is located on and formed continuously with a semiconductor layer, which is adapted to be formed into a source-and-drain region 3, 4 and a channel region 2, and then a second insulating film 6 and a gate electrode (hereinafter also called simply the gate)7 are located over the first insulating film 2 so as to cover the semiconductor layer and the island of the first insulating film 5. Now for reducing the threshold voltage as mentioned above, it becomes necessary to reduce the total thickness of the two-layer gate insulating film 5, 6. This is because reduction of the two layers increases the capacitance so that an adequate electric field effect can be obtained even at low voltage. Whereas the semiconductor layer, unlike the gate insulating film, cannot be thinned, partly because it should be doped with an impurity as by ion implantation and partly because an adequate process margin during laser crystallization should be secured. Consequently, if the gate insulating film is thinned in order to lower the threshold voltage as mentioned above, then the thickness of the second gate insulating film becomes smaller than the difference between the semiconductor layer and the first gate insulating film so that gate-leak-free covering is difficult to achieve. Thus short circuit (gate leak) would tend to occur between the gate and the source-and-drain region.
As a solution for these problems, the following method was proposed by Japanese Patent Laid-Open Publication No. Hei6-85258. As shown in FIG. 10 of the accompanying drawings of the present specification, a semiconductor film 12 is formed in an island shape on an insulator substrate 11 and then a first insulating film 13 is formed on the island-shape semiconductor film 12, whereupon a second insulating film 21 is formed so as to cover the stepped peripheral edges of such composite island of the semiconductor film 12 and first insulating film 13. And a gate electrode 14 is formed over the first insulating film 13 surrounded by the second insulating film 21, so the semiconductor film 12 and the gate 14 are perfectly isolated from each other, preventing occurrence of short circuit (gate leak) between the semiconductor film 12 and the gate 14, i.e., between the gate and the source-and-drain. To realize such structure, the second insulating film 21 has to be etched selectively, namely, at only the region directly above the island after having been formed along its entire surface over the first insulating film 13. As a consequence, the second insulating film 21 requires a material such that it can be selectively etched with respect to the first insulating film 13 or the second insulating film 21 requires a selective etching process. Especially when the first insulating film 13 is thinned further in an effort to improve the throughput and performance, a much higher selective ratio is needed, and a dry etching method free of plasma damage to either the gate insulating film or the insulating-film-and-semiconductor interface would be necessitated.
As an alternative method that ensures inter-electrode isolation using a two-layer insulating film, Japanese Patent Laid-Open Publication No. Hei6-61490 discloses a conventional two-layer technology which optimizes the thickness and cross-sectional shape of each layer and employs two highly dielectric thin films for securing high performance of a thin film transistor. As shown in FIG. 11, this conventional method aims to provide a well-insulating, highly reliable isolation structure by optimizing the shape of a second insulating film 1014b rather than the shape of a first insulating film 1014a, which covers gates 103a, 1013b. Further, the gate metal as a prospective lower electrode is covered with tungsten oxide and then a silicon nitride film for forming a good MIS interface with hydrogenated amorphous silicon, whereupon a hydrogenated amorphous silicon film and a source-and-drain layer are formed. This conventional covering method using the two-layer insulating film is effective in covering the stepped regions defined by only the gate electrode and semiconductor layer. However, this publication is totally silent about and even does not anticipate any second insulating film that covers the stepped edges of the island constituted by the semiconductor layer and the first gate insulating film.
As the low temperature formation technology for a gate insulating film in particular, developments of means for forming a silicon dioxide film by plasma CVD, sputtering or low pressure CVD have increasingly become popular. The silicon dioxide film, which is formed at such a low temperature of less than about 600xc2x0 as to enable the use of the above-described glass substrate, would be encountered with the following problems as compared to the thermally oxidized film to be used in the conventional LSI process.
For the bulk performance of the gate insulating film designated by (a) in FIG. 18 of the accompanying drawings of the present specification, it is required to reduce the defect level derived from residual stress, dangling bond, impurity or other cause and to improve the insulating strength.
For the high performance of interface with the silicon active layer constituting the channel designated by (b) in FIG. 18, it is required to reduce the interface level derived from incomplete cleaning, plasma damage, etc.
For covering the island""s stepped edges designated by (c) in FIG. 18, the island-shaped semiconductor layer has to be covered precisely.
In order to solve these problems, a method of minimizing plasma damage with improving the insulating strength by sputtering using a mixed gas of oxygen and argon as a discharge gas has been proposed by Japanese Laid-Open Publications Nos. Hei3-120871 and Hei3-241873. However, in sputtering, since the film-forming precursor strikes on the substrate at about right angles, precise covering over the stepped edges of the island is difficult to achieve.
Japanese Patent Laid-Open Publication No. Hei3-19340 discloses a method for increasing the film-forming rate gradually as the film formation progresses away from the semiconductor-and-insulating-film interface, by lowering the concentration of helium with time during plasma CVD.
Japanese Patent Laid-Open Publication No. Hei3-108319 disclosed a method for forming a good semiconductor-and-insulating-film interface by carrying out the formation of a semiconductor thin film and the formation of an insulating film in a common reaction vessel.
The above-mentioned scientific paper, i.e., IEEE ELECTRON DEVICE LETTERS, Vol. 15, No. 2, page 69, xe2x80x9cHigh Performance Polycrystalline Silicon Thin Film Transistor Fabricated Using Remote Plasma CVD of SiO2,xe2x80x9d by M. Sekiya, et al. Additionally discloses remote plasma CVD of silicon dioxide film formation for obtaining a good insulating-film-and-silicon interface. For forming a good semiconductor-and-insulating-film interface, plasma impact on the surface of a semiconductor, which constitutes a gate insulating film, is restricted by bringing a plasma forming region, which serves to assist film-forming reaction of the precursor and dissolution of gas, away from the substrate position.
In this conventional method, however, although a good interface can be formed, the insulating strength is yet low so that thinning of the gate insulating film in an effort to secure the necessary reliability of the device and to lower the threshold voltage would be difficult to achieve.
It is therefore an object of the present invention to provide a thin film transistor structure which increases the degree of freedom in designing the structure and in selecting the thin film materials in the manufacturing process and a method for manufacturing such thin film transistor structure and does not need a dry etching step, which requires high uniformity and reproductivity, thus realizing a thin film transistor that takes on a good MOS interface characteristic in a low-temperature process.
Another object of the invention is to provide a highly dielectric MOS structure without increasing the number of process steps and to provide, by a practical process, a thin film transistor which is operable by a low threshold voltage.
Still another object of the invention is to provide a thin film transistor which guarantees: using the chemical vapor deposition (CVD), which enables good step-coverage precision, and particularly plasma CVD rather than the physical vapor deposition, which is represented by sputtering high in directivity and not suitable in covering the stepped edges of the island, (1) lowering the defect level derived from residual stress, dangling bond, impurity, etc. and improving the insulating strength, (2) lowering the interface level derived from incomplete cleaning, plasma damage, etc., and (3) covering stepped edges of the island of semiconductor layers precisely.
A further object of the invention is to provide a method for manufacturing the thin film transistor described in the previous paragraph.
According to a first aspect of the present invention, in a thin film transistor comprising an insulator substrate, a semiconductor layer, which is formed on the insulator substrate in an island shape and is composed of channel, source and drain regions, a gate insulating film, and a gate electrode, after the gate insulating film has been formed, the gate insulating film is covered with the gate electrode from the upper side, as shown in FIGS. 1(a) to 1(c) and 2(a) to 2(c). The width of the gate insulating film at least in the B-Bxe2x80x2 direction transverse of the gate electrode is smaller than the width of the channel region. And the gate insulating film at least beneath the gate electrode is larger in thickness at the central region of the semiconductor layer than at the end regions of the semiconductor layer.
With this first transistor structure, it is possible to form a good interface between the insulating film and the silicon layer, as disclosed in IEEE ELECTRON DEVICE LETTERS, Vol. 15, No. 2, page 69, xe2x80x9cHigh Performance Polycrystalline Silicon Thin Film Transistor Fabricated Using Remote Plasma CVD of SiO2,xe2x80x9d by M. Sekiya, et al., and also to prevent gate leak in a simple manner without employing the step covering method disclosed in Japanese Patent Laid-Open Publication No. Hei6-85258. Namely, the stepped edges of the island-shape semiconductor layer are gentle in slope so that gate leak can be prevented there.
According to a second aspect of the invention, there is provided a thin film transistor comprising: an insulator substrate; a semiconductor layer formed on the insulator substrate in an island shape; a gate insulating film covering the semiconductor layer; and a gate electrode disposed over the gate insulating film; the gate insulating film being composed of a first gate insulating film layer, which is formed on the island of the semiconductor layer in an island shape analogous to the first-named island shape in such a manner that the first gate insulating film layer and the semiconductor layer jointly form a composite stepped island, and a second gate insulating film layer covering the composite stepped island, the first and second gate insulating film layers having different thicknesses d1, d2 which satisfy the following relation.
d1 less than d2.
With this second transistor structure, it is possible to prevent gate leak with good reproductivity.
According to a third aspect of the invention, the thicknesses d1, d2 of the first and second gate insulating film layers and a thickness dsi of the semiconductor layer satisfy the following relation.
dsi+d1 less than d2.
Also with this third transistor structure, it is possible to prevent gate leak with good reproductivity.
According to a fourth aspect of the invention, the gate insulating film is a laminate composed of two or more kinds of layers of different materials, and the material of one layer of the laminate defining an interface with the semiconductor layer is lower in permittivity than the material of the remaining at least one layer of the laminate. With this fourth transistor structure, it is possible to obtain the same drain current as conventional without increasing voltage applied to the gate even if the second insulating film is increased in thickness. Particularly in a preferable transistor structure in which the material of the first gate insulating film layer is silicone oxide and at least one of the materials of the remaining layers of the laminate is silicone nitride, it is possible to increase the thickness of the second insulating film without lowering the performance as compared to the case when the second insulating film is silicon dioxide, thus preventing gate leak.
According to a fifth aspect of the invention, there is provided a method for manufacturing a thin film transistor, comprising the steps of: forming a thin semiconductor film on an insulator substrate whose at least one surface is of an insulator; forming a first gate insulating film on the thin semiconductor film; etching the first gate insulating film at least one direction along a prospective gate electrode of the thin film transistor transverse of the first gate insulating film, with leaving unetched through a width smaller than the width of a prospective channel, source or drain of the thin film transistor; forming a second gate insulating film covering the first gate insulating film and the thin semiconductor film; and forming the gate on the second gate insulating film. Using this method, it is possible to obtain the first-named thin film transistor.
According to a sixth aspect of the invention, there is provided a method for manufacturing a thin film transistor, comprising the steps of: forming a thin semiconductor film on an insulator substrate whose at least one surface is of an insulator; forming a first gate insulating film on the thin semiconductor film; etching the first gate insulating film and the thin semiconductor film with leaving unetched regions as prospective channel, source and drain regions of the thin film transistor; forming a second gate insulating film covering the first gate insulating film and the thin semiconductor film; and forming a gate electrode on the second insulating film; the rate of the etching of the first gate insulating film being higher than that of the thin semiconductor film.
According to a seventh aspect of the invention, laser illumination takes place after at least one of the first and second gate insulating film layers has been formed on the thin semiconductor film. Since the thin semiconductor film and part of the gate insulating film formed on it are simultaneously exposed to laser, it is possible to treat the interface between the semiconductor and the insulating film with the heat generated due to laser absorption into the interface, thus forming the interface in a proper shape.
According to an eighth aspect of the invention, there is provided a thin film transistor comprising: an insulator substrate; a silicon active layer formed on the insulator substrate in an island shape; a gate insulating film covering the silicon active layer; and a gate electrode disposed over the gate insulating film; the gate insulating film being a silicon dioxide film containing at least two kinds of inert gas atoms different in mass number, the inert gas atoms smaller in mass number being contained in and near a first interface between the silicon dioxide silicon film and the silicon active layer, the inert gas atoms larger in mass number being contained in and near a second interface between the silicon dioxide film and the gate electrode.
In the present invention, the silicon active layer is a crystalline silicon layer from which prospective channel, source and drain regions of the thin film transistor are to be formed.
According to a ninth aspect of the invention, the gate insulating film of the thin film transistor can be obtained by a method for forming a silicon dioxide film on a silicon active layer of an insulator substrate by CVD, using a mixed gas containing a silicon compound, oxygen and a carrier gas, wherein the carrier gas comprises two or more kinds of inert gases, and the inert gas smaller (preferably smallest) in mass number is used at a starting stage of the silicon dioxide film formation while the inert gas larger than that smallest (or smaller) in mass number at a final stage of the silicon dioxide film formation. As CVD, particularly plasma CVD is preferable.
In this method, the stepped edges of the island can be covered with the insulating film precisely using CVD. Even assuming that plasma CVD is employed, since the impact is limited to light atoms or ions during formation of the insulating film near the interface with the silicon active layer, occurrence of plasma damage is reduced to a minimum, thus obtaining a high-performance of the interface. By supplying atoms or ions, which are larger in mass and hence have energy, to the surface of the growth during formation of the insulating film near the interface with the gate electrode, it is possible to increase the density of the insulating film by the particle impact, thus securing an excellent insulating strength. Accordingly the state of the interface with the silicon active layer is good and the resulting thin film transistor can take on the superb insulating strength.
According to a tenth aspect of the invention, the silicon dioxide film is a laminate composed of two or more layers, at least one of the layers contiguous to the silicon active layer containing the active gas atoms smallest in mass number, at least one of the remaining layers contiguous to the gate electrode containing the inert gas atoms larger in mass number than the inert gas atoms smallest in mass number. During formation of this silicon dioxide film, the kind of inert gas to be supplied may be changed with another, or the inert gas larger in mass number may be supplied in addition to the previous inert gas being supplied.
According to a eleventh aspect of the invention, the inert gas atoms smallest in mass number are contained in and near the first interface between the silicon dioxide film and the silicon active layer, and the active gas atoms larger in mass number than those smallest in mass number are contained in the silicon dioxide film in varying concentration continuously increasing from the first interface with the silicon active layer toward the second interface with the gate electrode. During formation of this silicon dioxide film, the amount of supply of the inert gas larger in mass number than those smallest in mass number may be progressively increased.
Most preferably, the inert gas atoms smallest in mass number are helium, and the inert gas atoms larger in mass number than helium are argon.
According to a twelfth aspect of the invention, there is provided a method for manufacturing a thin film transistor, comprising the steps of: forming a silicon active layer on a substrate whose at least top surface is an insulator; forming a first silicon dioxide layer on a top surface of the silicon active layer by CVD using a mixed gas containing a silicon compound, oxygen and a first inert gas as a carrier gas; etching the silicon active layer and the first silicon dioxide layer simultaneously in such a manner that regions of the silicon active layer, which are adapted to be prospective channel, source and drain regions of the thin film transistor, are left unetched and that the first silicon dioxide layer becomes smaller than each of the channel, source and drain regions; and forming a second silicon dioxide layer, which covers the first silicon dioxide layer and the silicon active layer, by CVD using a mixed gas containing a silicon compound, oxygen and a second active gas, which is larger in mass number than the first active gas, as a carrier gas.
According to this method, it is possible to secure a good interface performance with the silicon active layer by the first silicon dioxide film and to improve the insulation strength by the precisely formed second silicon dioxide layer, so that the peripheral edge of the island of the first silicon dioxide layer and silicon active layer can be covered with the second silicon dioxide layer very simply.